姓名:蘇彬
職稱: 教授
連絡電話:886-3-5712121 ext.54142
E-mail: [email protected]
簡介:
Prof. Pin Su received the B.S. and M.S. degrees in electronics engineering from National Chiao Tung University, and the Ph.D. degree from the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley.
From 1997 to 2003, he conducted his doctoral and postdoctoral research in Silicon-On-Insulator (SOI) devices at Berkeley. He was also one of the major contributors to the unified BSIMSOI model, the first industrial standard SOI MOSFET model for circuit design. Since August 2003, he has been with the Department of Electronics Engineering, National Chiao Tung University, where he is currently a Professor. His research interests include silicon-based nanoelectronics, modeling and design for exploratory/post CMOS devices for ultra-low-power applications, and circuit-device interaction and cooptimization in nanoscale CMOS. He has authored or coauthored over 70 refereed journal papers and 110 conference papers regarding his research interests. Prof. Su served in the technical committee of International Electron Devices Meeting (IEDM) from 2012 to 2013.
研究專長:
1.Silicon-Based Nanoelectronics (e.g. Random Variabilities and Quantum Confinement in Scaled Devices, etc.)
2.Modeling & Design for Exploratory/Post CMOS Devices (e.g. Tri-gate FinFET, III-V-on-Insulator and Tunnel FET, etc.)
3.Circuit and Device Interaction (e.g. Cell Stability of Low-Voltage SRAM, Devices with Monolithic-3D Integration, etc.)
職稱: 教授
連絡電話:886-3-5712121 ext.54142
E-mail: [email protected]
簡介:
Prof. Pin Su received the B.S. and M.S. degrees in electronics engineering from National Chiao Tung University, and the Ph.D. degree from the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley.
From 1997 to 2003, he conducted his doctoral and postdoctoral research in Silicon-On-Insulator (SOI) devices at Berkeley. He was also one of the major contributors to the unified BSIMSOI model, the first industrial standard SOI MOSFET model for circuit design. Since August 2003, he has been with the Department of Electronics Engineering, National Chiao Tung University, where he is currently a Professor. His research interests include silicon-based nanoelectronics, modeling and design for exploratory/post CMOS devices for ultra-low-power applications, and circuit-device interaction and cooptimization in nanoscale CMOS. He has authored or coauthored over 70 refereed journal papers and 110 conference papers regarding his research interests. Prof. Su served in the technical committee of International Electron Devices Meeting (IEDM) from 2012 to 2013.
研究專長:
1.Silicon-Based Nanoelectronics (e.g. Random Variabilities and Quantum Confinement in Scaled Devices, etc.)
2.Modeling & Design for Exploratory/Post CMOS Devices (e.g. Tri-gate FinFET, III-V-on-Insulator and Tunnel FET, etc.)
3.Circuit and Device Interaction (e.g. Cell Stability of Low-Voltage SRAM, Devices with Monolithic-3D Integration, etc.)