姓名: 莊紹勳
職稱: 講座教授
連絡電話:(03)573-1830
E-mail: [email protected]
簡介:
Steve S. Chung received his Ph.D. degree from the University of Illinois at Urbana-Champaign, in Electrical Engineering in 1985. His Ph.D.thesis advisor is the world-famous scholar and CMOS Co-Inventor, Prof. C. T. Sah.
Currently, he is an NCTU Chair Professor, UMC Research Chair Professor at the National Chiao Tung University (NCTU), where he worked as Dean of International Affairs,between 2007-2008. Between 2004-2005, he was the first Department Head of EECS Honors Program, to promote a new undergraduate program for academic excellence, at NCTU where he has served since 1987. He was a Visiting Professor with the University of California-Merced(2009-2010), a guest Instructor at Stanford (2009) and also a visiting scholar to Stanford University, CA, in 2001. He is an honorary professor of the Institue of Microelectronics, CAS. He was also the consultant to both TSMC and UMC on developing CMOS and flash memory technologies. His current research areas include CMOS device technology with emphasis on trigate and Tunneling FET, flash memory technology, resistance memory technology, reliability characterization and modeling. He has published more than 200 journal and conference papers, one textbook, and holds more than 20 patents in CMOS and flash memory. He and his Ph. D. student invented the IFCP(Incremental Frequency Charge Pumping) interface characterization method which is well suited for reliability diagnosis of 90nm and beyond CMOS devices with gate oxide thickness down to 1nm [Remark 1]. The merit of this method is its capability for replacing the conventional CV method that has been used for over 40+ years. Since 1995, he has presented more than 22 times in the world leading IEEE conferences, IEDM and VLSI, with focus on the reliability and technology of CMOS, flash memories. He was invited at 2008IEDM to give a talk, with topics in advanced CMOS related strain techniques, that has been used for the 65nm, 45nm,and beyond, a research supported by the world 2nd largest foundry-UMC.
He is an IEEE Fellow, a current Board Governor of EDS, an elected AdCom member (2004-2009), Distinguished Lecturer, Regions/Chapters Chair of EDS, and Editor of EDL (2002-2008). He has served on the committees of premiere conferences, e.g., VLSI Technology, IEDM, IRPS, IPFA, SSDM etc. For the first time in Taiwan history, at the 50th anniversary of IEEE, ED Taipei chapter was awarded the 2002 EDS Chapter of the Year Award under his leadership as the chapter chair. He was awarded 3 times Outstanding Research Award for excellence in research, as well as the top-PI in 2003, from the National Science Council, Taiwan. He has been granted NSC research fellow since 2006. He was also granted both Distinguished EE Professor and Engineering Professor by the Engineering Societies of Taiwan. Recently, he was awarded the prestigeous Pan Wen-Yuan Award to recognize his contributions in research.
各項榮譽與重要貢獻 (Honors/Awards & Major Achievements)-
潘文淵研究傑出獎(Pan Wen-Yuan Outstanding Research Award, 2013)
國科會傑出特約研究人員獎(NSC Distinguished esearch Fellow, 2013)
國科會傑出學者計畫主持人 (NSC Distinguished Research Fellow, 2009-2012)
IEEE Fellow (for contributions to the reliability of ultra-thin-oxide CMOS devices)
國科會特約研究人員獎(NSC Research Fellow, 2006-2009)
國科會三次傑出研究獎(Outstanding Research Award, 1996-2003)
國科會三次優等研究獎(Excellent Research Award, 1989-1995)
中國工程師學會傑出工程教授(Distnguished Engineering Professor)
電機工程師學會傑出電機工程教授(Distinguished EE Professor)
專利(patents): > 20 (3 pending)
論文發表(published paper): IEEE Journal and Conference Papers (more than 200)
IEDM/VLSI論文發表: (First author發表)23篇 (up to 2013.9)
1995 VLSI Technology 台灣首次上榜論文為本研究群發表 (The first paper contributed from Taiwan)
1997 VLSI Technology 台灣唯一上榜論文為本研究群發表 (The only paper contributed from Taiwan)
[Remark 2]
1995-2013 VLSI Technology 台灣各大學上榜論文統計, 37% 為本研究群發表 (第一作者)
2002 IEEE EDS Chapter of the Year Award 為莊教授擔任IEEE EDS Taipei Chapter會長期間, 50年來台灣地區分會第一次獲得榮譽 (台灣現有26個IEEE 分會)
IEDMS Best Paper Award (最佳論文獎) (1996)
IEDMS Best Paper Award (最佳論文獎) (2010)
[Remark 1] S. S. Chung et al., in Symposium on VLSI Tech., pp. 74-75, Hawaii, 2002. ( also, US patent, No. 6,746,883)
[Remark 2] S. S. Chung et al., in Symposium on VLSI Tech., pp. 111-112, Kyoto, 1997.
Citations:
Who’s who in the world, 1999, 2000, 2001 Editions
Who’s who in finance, 2000 Edition
Who’s who in Asia, 2006 Edition
研究專長:
1.先進奈米CMOS元件技術 (Advanced CMOS Technology in the sub-20nm era)
2.Trigate and Tunneling FET
3.快閃記憶體(Flash Memory, Resistance Memory) 技術及可靠性物理 (Physics and technology of flash memory)
4.奈米CMOS元件量測技術與分析 (Measurement technique and Reliability of CMOS devices)
職稱: 講座教授
連絡電話:(03)573-1830
E-mail: [email protected]
簡介:
Steve S. Chung received his Ph.D. degree from the University of Illinois at Urbana-Champaign, in Electrical Engineering in 1985. His Ph.D.thesis advisor is the world-famous scholar and CMOS Co-Inventor, Prof. C. T. Sah.
Currently, he is an NCTU Chair Professor, UMC Research Chair Professor at the National Chiao Tung University (NCTU), where he worked as Dean of International Affairs,between 2007-2008. Between 2004-2005, he was the first Department Head of EECS Honors Program, to promote a new undergraduate program for academic excellence, at NCTU where he has served since 1987. He was a Visiting Professor with the University of California-Merced(2009-2010), a guest Instructor at Stanford (2009) and also a visiting scholar to Stanford University, CA, in 2001. He is an honorary professor of the Institue of Microelectronics, CAS. He was also the consultant to both TSMC and UMC on developing CMOS and flash memory technologies. His current research areas include CMOS device technology with emphasis on trigate and Tunneling FET, flash memory technology, resistance memory technology, reliability characterization and modeling. He has published more than 200 journal and conference papers, one textbook, and holds more than 20 patents in CMOS and flash memory. He and his Ph. D. student invented the IFCP(Incremental Frequency Charge Pumping) interface characterization method which is well suited for reliability diagnosis of 90nm and beyond CMOS devices with gate oxide thickness down to 1nm [Remark 1]. The merit of this method is its capability for replacing the conventional CV method that has been used for over 40+ years. Since 1995, he has presented more than 22 times in the world leading IEEE conferences, IEDM and VLSI, with focus on the reliability and technology of CMOS, flash memories. He was invited at 2008IEDM to give a talk, with topics in advanced CMOS related strain techniques, that has been used for the 65nm, 45nm,and beyond, a research supported by the world 2nd largest foundry-UMC.
He is an IEEE Fellow, a current Board Governor of EDS, an elected AdCom member (2004-2009), Distinguished Lecturer, Regions/Chapters Chair of EDS, and Editor of EDL (2002-2008). He has served on the committees of premiere conferences, e.g., VLSI Technology, IEDM, IRPS, IPFA, SSDM etc. For the first time in Taiwan history, at the 50th anniversary of IEEE, ED Taipei chapter was awarded the 2002 EDS Chapter of the Year Award under his leadership as the chapter chair. He was awarded 3 times Outstanding Research Award for excellence in research, as well as the top-PI in 2003, from the National Science Council, Taiwan. He has been granted NSC research fellow since 2006. He was also granted both Distinguished EE Professor and Engineering Professor by the Engineering Societies of Taiwan. Recently, he was awarded the prestigeous Pan Wen-Yuan Award to recognize his contributions in research.
各項榮譽與重要貢獻 (Honors/Awards & Major Achievements)-
潘文淵研究傑出獎(Pan Wen-Yuan Outstanding Research Award, 2013)
國科會傑出特約研究人員獎(NSC Distinguished esearch Fellow, 2013)
國科會傑出學者計畫主持人 (NSC Distinguished Research Fellow, 2009-2012)
IEEE Fellow (for contributions to the reliability of ultra-thin-oxide CMOS devices)
國科會特約研究人員獎(NSC Research Fellow, 2006-2009)
國科會三次傑出研究獎(Outstanding Research Award, 1996-2003)
國科會三次優等研究獎(Excellent Research Award, 1989-1995)
中國工程師學會傑出工程教授(Distnguished Engineering Professor)
電機工程師學會傑出電機工程教授(Distinguished EE Professor)
專利(patents): > 20 (3 pending)
論文發表(published paper): IEEE Journal and Conference Papers (more than 200)
IEDM/VLSI論文發表: (First author發表)23篇 (up to 2013.9)
1995 VLSI Technology 台灣首次上榜論文為本研究群發表 (The first paper contributed from Taiwan)
1997 VLSI Technology 台灣唯一上榜論文為本研究群發表 (The only paper contributed from Taiwan)
[Remark 2]
1995-2013 VLSI Technology 台灣各大學上榜論文統計, 37% 為本研究群發表 (第一作者)
2002 IEEE EDS Chapter of the Year Award 為莊教授擔任IEEE EDS Taipei Chapter會長期間, 50年來台灣地區分會第一次獲得榮譽 (台灣現有26個IEEE 分會)
IEDMS Best Paper Award (最佳論文獎) (1996)
IEDMS Best Paper Award (最佳論文獎) (2010)
[Remark 1] S. S. Chung et al., in Symposium on VLSI Tech., pp. 74-75, Hawaii, 2002. ( also, US patent, No. 6,746,883)
[Remark 2] S. S. Chung et al., in Symposium on VLSI Tech., pp. 111-112, Kyoto, 1997.
Citations:
Who’s who in the world, 1999, 2000, 2001 Editions
Who’s who in finance, 2000 Edition
Who’s who in Asia, 2006 Edition
研究專長:
1.先進奈米CMOS元件技術 (Advanced CMOS Technology in the sub-20nm era)
2.Trigate and Tunneling FET
3.快閃記憶體(Flash Memory, Resistance Memory) 技術及可靠性物理 (Physics and technology of flash memory)
4.奈米CMOS元件量測技術與分析 (Measurement technique and Reliability of CMOS devices)